The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device and a manufacturing method thereof which improves data retention.
In general, a nonvolatile semiconductor memory of the floating gate type includes an electrically insulated floating gate electrode underneath the control gate electrode, and charges are induced into the floating gate electrode to be retained as stored information. In the nonvolatile semiconductor memory of the floating gate type, when information is written or erased, a strong electric field is applied to the thin gate oxide film under the floating gate electrode, and charges are injected into or emitted from the floating gate electrode through the thin gate oxide film. Thus, the endurance in the writing and erasing of the information depends on the electric field of the gate oxide film formed under the floating gate electrode.
Such floating gate type nonvolatile semiconductor memories include EPROMs, EEPROMs, flash EEPROMs, etc. FIG. 1 shows a cross-sectional view of a conventional semiconductor memory cell structure of the typical floating gate type. In the cell shown in FIG. 1, a source region 9a and a drain region 9b, doped with an n.sup.+ impurity near the surface of a p-type silicon substrate 1, are separated from each other by a channel region. A thin gate oxide film 3 is formed on the channel region and is partially on both the source region 9a and the drain region 9b. The first conductive layer 4, which is provided as a floating gate electrode, the insulating film 5, and the second conductive, which is layer 6 provided as a control gate electrode are formed on the gate oxide film 3. To write information in an EPROM having such a cell structure, high voltages of 12.5 V and 7 to 8 V are respectively supplied to the control gate electrode and the drain region, thereby generating an electric field in the floating gate electrode and accelerating electrons in the pinch-off region on the drain region side and causing them to be injected into the floating gate electrode. When an ultraviolet ray is irradiated to erase the information, the injected electrons are emitted to initialize the memory cell. However, in a EEPROM, if a high voltage (about +20 V) is supplied to a control gate electrode with the drain grounded, electrons are injected into the floating gate electrode through a thin gate oxide film. Conversely, if the voltage is supplied to the drain with the control gate electrode grounded, electrons are emitted through the thin gate oxide film from the floating gate electrode. As described above, the injection and the emission of the electrons are carried out through the gate oxide film, resulting in a variation of the threshold voltage in the channel region, thereby obtaining the nonvolatile information memory function.
In a conventional nonvolatile semiconductor memory of the floating gate type, since the injection and the emission of the electrons are carried out by a hot electron or tunneling effect, a thin gate oxide film should be formed to effectively carry out the injection and the emission of the electrons. Conventionally, an EPROM has a thickness of approximately 300 .ANG. and a EEPROM has a thickness of 100 .ANG..
In such conventional nonvolatile semiconductor memories of the floating gate type, the electrons injected into the floating gate electrode when writing information are enclosed by the potential barrier resulting from the surrounding insulating film, hence stored. However, if the surrounding insulating film is damaged during the fabrication process or has a defect, the injected electrons leak through the damaged or defected portion. Electron leakage from the floating gate electrode deteriorates the reliability of the memory device.
To determine the main reason for this electron leakage, the information is stored in two samples having an interlayer insulating film thickness of 400 .ANG. and 600 .ANG.. Then the samples are baked for 48 hours at 200.degree. C. The variation in threshold voltage Vt is checked at 12 hour intervals and the result is obtained as a graphic diagram shown in FIG. 2, which shows that regardless of the interlayer insulating film thickness, the initial threshold voltages Vt of both samples decrease from +4 V to approximately +2 V over 48 hours. Therefore, the electron leakage of the floating gate electrode is not related to the thickness of the interlayer insulating film, and mainly occurs through the thin gate oxide film.
In the conventional cell structure shown in FIG. 1, a thin gate oxide film 3, a first conductive layer 4, an interlayer insulating film 5, and a second conductive layer 6 are sequentially stacked on a silicon substrate 1, and the second conductive layer 6, the interlayer insulating film 5, and the first conductive layer 4 are sequentially etched to form a stacked floating gate electrode and control gate electrode. At this time, if the etching is excessive, the edges of the gate oxide film 3 under the floating gate electrode 4 are also etched somewhat, or the exposed edges of the gate oxide film 3 receive an impulse and are then damaged by the responsive ions during reactive ion etching. Accordingly, the exposed edges of the gate oxide film 3 are damaged during the fabrication process, which causes the majority of electron leakage.
Specifically, in the case of flash EEPROMs, the gate oxide film is about 100 .ANG. thick, and in highly integrated devices, in the megabit region or more, the thickness of the insulating film is further decreased, so it is highly desirable to solve the problem of the data loss by electron leakage.